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CPU(4) Device Drivers Manual (hppa) CPU(4)

NAME

cpuHP PA-RISC CPU

SYNOPSIS

cpu* at mainbus0 irq 31

DESCRIPTION

The following table lists the PA-RISC CPU types and their characteristics, such as TLB, maximum cache sizes (where the ‘*’ character means on-chip) and HP 9000/700 machines they were used in (see also intro(4) for the reverse list).
CPU PA Clock Caches TLB BAT Models
MHz max KB max
7000 1.1a 66 256 L1I 96I 4I 705, 710, 720
256 L1D 96D 4D 730, 750
7100 1.1b 100 1024 L1I 120 16 715/33/50/75
2048 L1D 725/50/75
{735,755}/100
742i, 745i, 747i
7150 1.1b 125 1024 L1I 120 16 735/125, 755/125
2048 L1D
7100LC 1.1c 100 1 L1I* 64 8 712/60/80/100
1024 L2I 715/64/80/100
1024 L2D 715/100XC
725/64/100
743i, 748i
SAIC
7200 1.1d 140 2 L1* 120 16 C100, C110
1024 L2I J200, J210
1024 L2D
7300LC 1.1e 180 64 L1I* 96 8 A180, A180C
64 L1D* B132, B160, B180
8192 L2 C132L, C160L
744, 745, 748
RDI PrecisionBook
8000 2.0 180 1024 L1I 96 C160, C180
1024 L1D J280, J282
8200 2.0 300 2048 L1I 120 C200, C240
2048 L1D J2240
8500 2.0 440 512 L1I* 160 A400, A500, C360
1024 L1D* B1000, B2000, C3000
J5000, J7000
8600 2.0 550 512 L1I* 160 A400, A500, C3600
1024 L1D* B2000, B2600
J5600, J6000, J7600
8700 2.0 875 768 L1I* 240 A400, A500, J6700
1536 L1D* C3650, C3700, C3750

FLOATING-POINT COPROCESSOR

The following table summarizes available floating-point coprocessor models for the 32-bit PA-RISC processors.
FPU Model
Indigo
Sterling I MIU (TYCO)
Sterling I MIU (ROC w/Weitek)
FPC (w/Weitek)
FPC (w/Bit)
Timex-II
Rolex 725/50, 745i
HARP-I
Tornado J2x0,C1x0
PA-50 (Hitachi)
PCXL 712/60/80/100

SUPERSCALAR EXECUTION

The following table summarizes the superscalar execution capabilities of 32-bit PA-RISC processors.
CPU Units Bundles
7100 1 integer ALU load-store/fp
1 FP int/fp
branch/*
7100LC 2 integer ALU load-store/int
1 FP load-store/fp
int/fp
branch/*
7200 2 integer ALU load-store/int
1 FP load-store/fp
int/int
int/fp
branch/*
7300LC 2 integer ALU load-store/int
1 FP load-store/fp
int/fp
branch/*
8x00 2 integer ALU 4-way superscalar
2 shift/merge
2 load/store
2 FPU mul/add
2 FPU div/sqrt
In conclusion, all of the above CPUs are dual-issue, or 2-way superscalar, with the exception that on CPUs with two integer ALUs only one of these units is capable of doing shift, load/store and test operations. Additionally, there are several kinds of restrictions placed upon the superscalar execution:
For the purpose of showing which instructions are allowed to proceed together through the pipeline, they are divided into classes:
Class Description
flop floating point operation
ldst loads and stores
flex integer ALU
mm shifts, extracts and deposits
nul might nullify successor
bv BV, BE
br other branches
fsys FTEST and FP status/exception
sys system control instructions
For CPUs with two integer ALUs (7100LC, 7200, 7300LC), the following table lists the instructions which are allowed to be executed concurrently:
First Second instruction
flop + ldst/flex/mm/nul/bv/br
ldst + flop/flex/mm/nul/br
flex + flop/ldst/flex/mm/nul/br/fsys
mm + flop/ldst/flex/fsys
nul + flop
sys never bundled
ldst + ldst is also possible under certain circumstances, which is then called "double word load/store".
The following restrictions are placed upon the superscalar execution:

PERFORMANCE MONITOR COPROCESSOR

The performance monitor coprocessor is an optional, implementation-dependent coprocessor which provides a minimal common software interface to implementation-dependent performance monitor hardware.

DEBUG SPECIAL UNIT

The debug special function unit is an optional, architected SFU which provides hardware assistance for software debugging using breakpoints. The debug SFU is currently defined only for Level 0 processors.

SEE ALSO

asp(4), intro(4), lasi(4), mem(4), pdc(4), wax(4)
Hewlett-Packard, PA-RISC 1.1 Architecture and Instruction Set Reference Manual, May 15, 1996.
Hewlett-Packard, PA7100LC ERS, Public version 1.0, March 30 1999.
Hewlett-Packard Journal, Design of the PA7200 CPU, February 1996.
Hewlett-Packard, PA7300LC ERS, Version 1.0, March 18 1996.

HISTORY

The cpu driver was written by Michael Shalayeff <mickey@openbsd.org> for the HPPA port for OpenBSD 2.5.
February 14, 2014 OpenBSD-current