NAME

SYNOPSIS

DESCRIPTION

• Core bus controller
• System clock
• Interrupt controller
• DMA controller
• Real-time clock Interface
• RAM and EEPROM controllers

The irq level supplied is hardwired to the CPU pin, so changing the value would not produce any noticeable results (except lost interrupts for the whole I/O subsystem).

MACHINES

• 705, 710
• 715/{33,50,75}
• 725/{50,75}
• 720, 730, 750
• 735/*
• 745i/{50,75}
• 747i/{50,75}
• 755/*

SEE ALSO

Hardball I/O Subsystem ERS, Revision 1.1, Hewlett-Packard, 30 September 1991.

HISTORY